Semiconductor device having a ferroelectric capacitor and a fabrication process thereof

ABSTRACT

A method of fabricating a semiconductor device having a ferroelectric capacitor includes the steps of forming a lower electrode layer of the ferroelectric capacitor on an insulation film covering an active device element, forming a ferroelectric film on the lower electrode layer as a capacitor insulation film, crystallizing the ferroelectric film by applying a thermal annealing process in an atmosphere containing a non-oxidizing gas and an oxidizing gas, and forming an upper electrode layer on the ferroelectric film.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present invention is a continuation-in-part application ofthe U.S. patent application 09/429,984 filed on Oct. 29, 1999.

BACKGROUND OF THE INVENTION

[0002] The present invention generally relates to semiconductor devicesand more particularly to a semiconductor memory device having aferroelectric capacitor.

[0003] Semiconductor devices such as DRAMs and SRAMs are usedextensively in various information processing apparatuses includingcomputers as a high-speed main memory device. These conventionalsemiconductor devices, however, are volatile in nature and theinformation stored therein is lost when the electric power is turnedoff. Thus, it has been practiced in conventional computers and computersystems to use magnetic disk devices as a large capacity, auxiliarystorage device for storing programs and data.

[0004] However, magnetic disk devices are bulky and fragile, and areinherently vulnerable to mechanical shocks. Further, magnetic diskdevices generally have drawbacks of large electrical power consumptionand low access speed.

[0005] In view of the problems noted above, there is an increasingtendency in computers and computer systems of using flash-memory devicesfor the non-volatile auxiliary storage device. A flash-memory device isa device having a construction similar to that of a MOS transistor andstores information in an insulated floating gate in the form ofelectrical charges. It should be noted that flash-memory devices have aconstruction suitable for monolithic integration on a semiconductor chipin the form of an LSI. Thus, there are attempts to construct alarge-capacity storage device comparable to a magnetic disk device byusing a flash-memory.

[0006] In a flash-memory device, writing of information is achieved bytunneling of hot electrons through a tunneling insulation film into thefloating gate electrode. Further, erasing of the information is achievedalso by causing the electrons in the floating gate to tunnel to a sourceregion or to a channel region through the tunneling insulation film.Thus, a flash-memory device has an inherent drawback in that it takes asubstantial time for writing or erasing information. Further, aflash-memory device generally shows the problem of deterioration of thetunneling insulation film after a repeated writing and erasingoperations. When the tunneling insulation film is deteriorated, thereading or erasing operation becomes unstable and unreliable. An EEPROM,having a similar construction to a flash-memory, has a similar problem.

[0007] In view of the various drawbacks of the foregoing conventionalnon-volatile semiconductor devices, there is a proposal of aferroelectric semiconductor memory device designated hereinafter asFeRAM for the auxiliary memory device and further for the high-speedmain memory device of a computer. A ferroelectric semiconductor memorydevice stores information in a ferroelectric capacitor insulation filmin the form of spontaneous polarization.

[0008] A ferroelectric semiconductor memory device typically includes amemory cell transistor and a memory cell capacitor similarly to a DRAM,wherein the memory cell capacitor uses a ferroelectric material such asPZT (Pb(Zr,Ti)O₃) or PLZT ((Pb,La)(Zr,Ti)O₃) for the capacitorinsulation film. Thus, the ferroelectric semiconductor memory device issuitable for monolithic integration to form an LSI.

[0009] As the ferroelectric semiconductor memory device carries out thewriting of information by controlling the spontaneous polarization ofthe ferroelectric capacitor insulation film, the writing is achievedwith a high speed, faster by a factor of 1000 or more than the case of aflash-memory. As noted before, the writing of information is achieved ina flash-memory by injecting hot electrons into the floating gate throughthe tunneling insulation film. As the control of the polarization isachieved by simply applying a voltage, the power consumption is alsoreduced below about 1/10 as compared with the case of a flash-memory.Further, the ferroelectric semiconductor memory device, lacking thetunneling insulation film, provides an increased lifetime of one hundredthousand times as large as the lifetime of a flash-memory device.

[0010] Currently, FeRAMs are fabricated according to a relatively easydesign rule of about 1 μm. On the other hand, investigation is beingmade for increasing the tightness of the design rule so as to enableintegration of the FeRAMs with other high-speed submicron devices suchas CMOS logic devices on a common semiconductor chip.

[0011]FIG. 1 shows the construction of a conventional FeRAM 10.

[0012] Referring to FIG. 1, the FeRAM 10 includes a memory celltransistor constructed on a Si substrate 11, which may be any of thep-type or n-type. The half of the cell structure is represented in FIG.1, wherein it should be noted that the process used in FIG. 1 is nothingmore than an ordinary CMOS process. Thus, a p-type well 11A is formed ona Si substrate 11, on which an active region is defined by a field oxidefilm 12. On the Si substrate 11, there is provided a gate electrode 13in correspondence to the foregoing active region, wherein the gateelectrode 13 constitutes the word line of the FeRAM. Further, a gateoxide film not illustrated is interposed between the Si substrate 11 andthe gate electrode 13, and diffusion regions 11B and 11C of the n⁺-typeare formed in the p-type well 11A at both lateral sides of the gateelectrode 13 as the source region and the drain region of the memorycell transistor. Thereby, a channel region is formed in the p-type well11A between the diffusion region 11B and the diffusion region 11C.

[0013] It should be noted that the gate electrode 13 is covered by a CVDoxide film 14 provided so as to cover the surface of the Si substrate 11in correspondence to the active region. A lower electrode 15 having aPt/Ti structure is deposited on the CVD oxide film 14, wherein the lowerelectrode 15 constitutes the drive line of the FeRAM.

[0014] A ferroelectric insulation film 16 of PZT or PLZT covers thelower electrode 15, and an upper electrode 17 of Pt is formed on theferroelectric capacitor insulation film 16.

[0015] It should be noted that the lower electrode 15, the ferroelectricinsulation film 16 and the upper electrode 17 form together aferroelectric capacitor. The ferroelectric capacitor as a whole iscovered by another interlayer insulation film 18.

[0016] A contact hole 18A is formed in the interlayer insulation film 18so as to expose the upper electrode 17, and contact holes 18B and 18Care formed further in the interlayer insulation films 18 and 14 so as toexpose the diffusion regions 11B and 11C, respectively.

[0017] The local interconnection pattern 19A is formed by an Al-alloysuch that the local interconnection pattern 19A connects the contacthole 18A and the contact hole 18B electrically.

[0018] There is provided a bit line pattern 19B of an Al-alloy on theinterlayer insulation film 18 so as to make an electrical contact withthe diffusion region 11C at the contact hole 18C. The localinterconnection pattern 19A and the bit line 19B are covered by apassivation film 20.

[0019]FIG. 2 shows the hysteresis appearing in the polarization of aPLZT film constituting the foregoing ferroelectric capacitor insulationfilm 16.

[0020] Referring to FIG. 2, it will be noted that the PLZT film 16experiences an inversion of polarization when a predetermined writevoltage is applied between the lower electrode 15 and the upperelectrode 17 such that a predetermined electric field is applied to thePLZT film 16. In other words, desired information is written into thePLZT film 16 in the form of binary data by applying the write voltageacross the upper electrode 17 and the lower electrode 15. Further,reading of the information thus written into the PLZT film 16 isachieved by detecting the conduction or no-conduction of the memory celltransistor, wherein such a detection is made by activating the foregoingword line, and hence the gate electrode 13, and further by detecting thevoltage appearing at the bit line electrode 19B.

[0021] Larger the value of the spontaneous polarization represented inFIG. 2 by 2Pr, the more the reliability of the retention of informationin the PLZT film 16. Further, the magnitude of the electric field neededto cause a writing of information decreases with increasing value of2Pr. In other words, increase of the spontaneous polarization 2Prcontributes to the decrease of the drive voltage of the FeRAM 10. Thus,there is a demand for increasing the value of the spontaneouspolarization 2Pr in the FeRAM 10 of FIG. 1.

[0022] It should be noted that the semiconductor memory device of FIG. 1can be used also for a DRAM. In this case, due to the very largerelative dielectric constant of the ferroelectric capacitor insulationfilm 16, a sufficient capacitance is secured without using a complicatedshape and process for forming the memory cell capacitor.

[0023] In general, it is known that the ferroelectric properties of aPZT or PLZT film is related to the orientation of the PZT or PLZTcrystals constituting the film. Commonly, a predominantly <111> - or<100>-orientation is obtained for a PZT or PLZT film formed on a Ptlower electrode, which has a self-textured <111>-orientation, due to theepitaxial effect, in which the surface energy is minimized as a resultof the foregoing film orientation. It should be noted that a PZT or PLZTfilm has a self-textured <100>-orientation. In order to maximize theremnant polarization of the PZT or PLZT film, it is desired to align thePZT of PLZT crystals, which belong to the tetragonal crystal system,such that the switching direction for the preferential <100> orientationis perpendicular to the switching electric field.

[0024] Meanwhile, it is known that the PZT or PLZT film constituting theferroelectric capacitor insulation film 16 of FIG. 1 shows a columnarmicrostructure and that the value of the spontaneous polarization 2Pr ismaximized when the crystal grains therein are oriented in the <111>direction.

[0025] In the formation of the ferroelectric capacitor as noted above,it is very important to crystallize the ferroelectric capacitorinsulation film 16 by conducting a crystallization process. Without sucha crystallization process, no desirable property is obtained for theferroelectric capacitor.

[0026] Conventionally, such a ferroelectric capacitor is formed first byforming the adhesion layer of the Ti and then the lower electrode 15 ofPt by a sputtering process conducted on the interlayer insulation film14 in a reducing atmosphere. Next, the ferroelectric capacitorinsulation film 16 of PZT or PLZT is formed on the lower electrode 15 bya sputtering process or a sol-gel process.

[0027] Next, the ferroelectric capacitor insulation film 16 is subjectedto a thermal annealing process in an oxidizing atmosphere at atemperature of typically 700-800° C., and the ferroelectric capacitorinsulation film 16 thus formed undergoes a crystallization. Thereby, ithas been practiced to conduct the crystallization process in anoxidizing atmosphere so that the formation of oxygen defects in theferroelectric capacitor insulation film 16, caused as a result ofdiffusion of oxygen atoms from the ferroelectric capacitor insulationfilm 16 to the lower electrode 15, is successfully compensated for. As aresult of the crystallization, the ferroelectric capacitor insulationfilm 16 shows a preferable hysteresis as represented in FIG. 2, with aspontaneous polarization 2Pr.

[0028] On the other hand, in such a process of crystallizing theferroelectric capacitor insulation film 16, it has been discovered thatthere occurs an extensive counter diffusion of Pt and O at the boundarybetween the lower Pt electrode 15 and the ferroelectric capacitorinsulation film 16. More specifically, Pt from the lower electrode 15penetrates into the ferroelectric capacitor insulation film 16 and Ofrom the ferroelectric capacitor insulation film 16 penetrates into thelower electrode 15.

[0029] In order to avoid the foregoing problem of mutual diffusion, itis proposed to crystallize the ferroelectric capacitor insulation film16 by RTA processes first conducted in an inert atmosphere and thenconducted in an oxidizing atmosphere. By conducting the first RTAprocess in an inert atmosphere, the lower electrode 15 undergoesdensification and the foregoing problem of counter diffusion of Pt and Ois effectively suppressed.

[0030] Further, such a two-step annealing process suppresses themigration of Ti from the Ti adhesion layer to the surface of the lowerelectrode 15 through the grain boundary of Pt crystals constituting thelower electrode 15, wherein the Ti atoms thus reached the surface of thelower electrode 15 act as a nuclei for the <100> growth of theferroelectric capacitor insulation film 16.

[0031] On the other hand, in the experimental investigation on such aferroelectric capacitor formed by the two-step annealing process hasrevealed the fact that the ferroelectric capacitor insulation film thusformed tend to show a peeling, particularly in the marginal part of thesemiconductor wafer where there is a shadow ring for preventingdeposition of Pt on such marginal part of the semiconductor wafer. Itshould be noted that the semiconductor wafer is covered by a Ti filmuniformly, while the deposition of Pt on such marginal part is preventedby the shadow ring so as to avoid unwanted deposition of Pt to the rearside of the wafer. As a result of the use of the shadow ring, thethickness of the Pt film constituting the lower electrode 15 decreasestoward the marginal part of the semiconductor wafer, while it is notedthat the problem of the peeling of the ferroelectric capacitorinsulation film 16 occurs preferentially on such marginal part of thesemiconductor wafer.

[0032] When such peeling occurs, the yield of production of thesemiconductor device is deteriorated substantially.

SUMMARY OF THE INVENTION

[0033] Accordingly, it is a general object of the present invention toprovide a novel and useful semiconductor device having a ferroelectriccapacitor and a fabrication process thereof wherein the foregoingproblems are eliminated.

[0034] Another and more specific object of the present invention is toprovide a semiconductor device having a ferroelectric capacitor whereinthe problem of peeling of the ferroelectric capacitor insulation film iseffectively eliminated.

[0035] Another object of the present invention is to provide afabrication process of a semiconductor device having a ferroelectriccapacitor, comprising the steps of:

[0036] forming an insulation film over a substrate;

[0037] forming a lower electrode layer of said ferroelectric capacitorover said insulation film;

[0038] forming a ferroelectric film on said lower electrode layer as acapacitor insulation film of said ferroelectric capacitor;

[0039] crystallizing said ferroelectric film by applying a thermalannealing process in an atmosphere containing a non-oxidizing gas and anoxidizing gas; and

[0040] forming an upper electrode layer on said ferroelectric film.

[0041] Another object of the present invention is to provide a method offabricating a semiconductor device having a ferroelectric capacitor,comprising the steps of:

[0042] forming an active device element on a substrate;

[0043] forming an insulation film over said substrate to cover saidactive device element;

[0044] forming a lower electrode layer of said ferroelectric capacitorover said insulation film;

[0045] forming a ferroelectric film on said lower electrode layer as acapacitor insulation film of said ferroelectric capacitor;

[0046] crystallizing said ferroelectric film by applying a thermalannealing process in an atmosphere of an oxidizing gas under a reducedtotal pressure smaller than an atmospheric pressure; and

[0047] forming an upper electrode layer on said ferroelectric film.

[0048] Another object of the present invention is to provide asemiconductor device, comprising:

[0049] an insulation film provided over a substrate;

[0050] a lower electrode provided over said insulation film;

[0051] a ferroelectric film provided on said lower electrode, saidferroelectric film having a columnar microstructure extending from aninterface between said lower electrode and said ferroelectric film in adirection substantially perpendicular to a principal surface of saidlower electrode, said ferroelectric film essentially consisting ofcrystal grains having a generally uniform grain diameter of less thanabout 200 nm; and

[0052] an upper electrode provided on said ferroelectric film.

[0053] According to the present invention, the problem of peeling of theferroelectric film is effectively eliminated by conducting thecrystallization process in a mixed atmosphere of oxidizing gas andnon-oxidizing gas. As a result of such a crystallization process, thereappears a characteristic columnar microstructure in the ferroelectricfilm characterized by a generally uniform grain diameter of less thanabout 200 nm. By applying a further thermal annealing process to theferroelectric film thus obtained in an oxidizing atmosphere, the oxygendefects in the ferroelectric film are effectively compensated for, andthe ferroelectric film shows the desired large spontaneous polarization.

[0054] By conducting the crystallization process in an atmospherecontaining oxygen in addition to an inert gas or a non-oxidizing gas, itis believed that the Ti atoms thus migrated through the lower electrodeand reached the surface thereof undergoes oxidation and form achemically stable compound. Thus, when the ferroelectric film is formedon the lower electrode, the ferroelectric film is maintained stably onthe lower electrode, as there occurs no further oxidation, andassociated swelling, in the Ti compound formed on the top surface of thelower electrode, even when the oxidizing process is applied to theferroelectric film. Thereby, the problem of peeling of the ferroelectricfilm is successfully eliminated. As the atmosphere during thecrystallization is still predominantly inert, in spite of the fact thatthe oxidizing gas is admixed to the non-oxidizing gas, there occurs adensification in the lower electrode during the crystallization processof the ferroelectric film, and the problem of counter diffusion of Ptand O at the interface between the ferroelectric film and underlyinglower electrode is also suppressed.

[0055] The ferroelectric film thus formed has a columnar microstructureand the crystal grains therein are aligned predominantly in the <111>direction. Thereby, the ferroelectric capacitor thus formed shows amaximum spontaneous polarization 2Pr.

[0056] Other objects and further features of the present invention willbecome apparent from the following detailed description when read inconjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0057]FIG. 1 is a diagram showing the construction of a conventionalFeRAM;

[0058]FIG. 2 is a diagram showing a hysteresis loop of a ferroelectricmaterial used for an FeRAM;

[0059]FIGS. 3A and 3B are diagrams showing the construction of aferroelectric capacitor used in the experiments constituting the basisof the present invention as a test piece, according to a firstembodiment of the present invention;

[0060]FIGS. 4A and 4B are diagrams showing the RTA temperature profileused in the foregoing experiments;

[0061]FIGS. 5A and 5B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0062]FIGS. 6A and 6B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0063]FIGS. 7A and 7B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0064]FIGS. 8A and 8B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0065]FIGS. 9A and 9B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0066]FIGS. 10A and 10B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0067]FIGS. 11A and 11B are diagrams showing the surface morphology andcross-sectional morphology of the ferroelectric film obtained in anexperiment;

[0068]FIG. 12 is a diagram showing the surface morphology of theferroelectric film obtained in an experiment;

[0069]FIG. 13 is a diagram showing the switching electric charges of theferroelectric capacitor for various RTA conditions;

[0070]FIG. 14 is a diagram showing the saturation voltage of theferroelectric capacitor for various RTA conditions;

[0071]FIG. 15 is a diagram showing the volume fraction of the<111>-oriented crystals in the ferroelectric film of the ferroelectriccapacitor for various RTA conditions;

[0072]FIG. 16 is a diagram showing the volume fraction of the<100>-oriented crystals in the ferroelectric film of the ferroelectriccapacitor for various RTA conditions;

[0073]FIG. 17 is a diagram showing the volume fraction of the<111>-oriented crystals in the ferroelectric film of the ferroelectriccapacitor crystallized under various temperatures in a reduced pressureenvironment according to a second embodiment;

[0074]FIG. 18 is a diagram showing the volume fraction of the<111>-oriented crystals in the ferroelectric film of the ferroelectriccapacitor crystallized under various reduced pressure conditions;

[0075]FIG. 19 is a diagram showing the switching electric charge of theferroelectric capacitor for various annealing temperatures conductedunder a reduced pressure environment for crystallizing the ferroelectricfilm;

[0076]FIG. 20 is a diagram showing the saturation voltage of theferroelectric capacitor for various annealing temperatures conductedunder a reduced pressure environment for crystallizing the ferroelectricfilm;

[0077]FIGS. 21A and 21B are diagrams showing a two-layer structure and amechanism of the same; and

[0078] FIGS. 22A-22R are diagrams showing the fabrication process of asemiconductor device according to a third embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0079] [FIRST EMBODIMENT]

[0080] Hereinafter, the experiments conducted by the inventor of thepresent invention and constituting the basis of the present inventionwill be explained as a first embodiment of the present invention.

[0081]FIGS. 3A and 3B are diagrams showing the fabrication process of aferroelectric capacitor test piece 30 used in the foregoing experiment.

[0082] Referring to FIG. 3A, a SiO₂ film 32 is formed on a Si substrate31 by a thermal oxidation process with a thickness of 200 nm, forexample, and a lower electrode 33 of Pt is formed on the SiO₂ film 32 bya D.C. sputtering process conducted at a room temperature, with anadhesion layer 33A of Ti interposed between the SiO₂ film 32 and thelower electrode 33.

[0083] More specifically, the Ti adhesion layer 33A is formed in an Aratmosphere under the pressure of 0.7 Pa with a thickness of about 20 nmas represented in TABLE I below. Further, the lower electrode 33 of Ptis formed under the same condition with a thickness of about 175 nm. Thedeposition of the Ti film 33A is conducted by setting the D.C. plasmapower to 2.6 kW, wherein the deposition of the Ti film 33A is conductedfor the duration of 9 seconds while the deposition of the lowerelectrode 33 is conducted for the duration of 96 seconds while settingthe D.C. plasma power to 1.0 kW. TABLE I Ar pressure DC power durationthickness (Pa) (kW) (second) (nm) Ti 0.7 2.6  9  20 Pt 0.7 1.0 96 175

[0084] After the formation of the lower electrode 33, a PLZT film 34 isdeposited thereon by an R.F. sputtering process conducted at the roomtemperature under the pressure of 1.1 Pa with a thickness of typicallyabout 200 nm as represented in TABLE II below.

[0085] Referring to TABLE II, it will be noted that the R.F. sputteringis conducted by setting the R.F. plasma power to 1.0 kW and continuedfor the duration of 434 seconds. TABLE II Ar pressure RF power durationthickness (Pa) (kW) (seconds) (nm) 1.1 1.0 434 200

[0086] Next, the structure thus obtained is subjected to a thermalannealing process conducted at 600° C. for 90 seconds in variousatmospheres as represented in TABLE III below, with an RTA temperatureprofile of 125° C./sec as represented in FIG. 4A.

[0087] Referring to FIG. 4A, the substrate 31 thus covered with the PLZTfilm 34 is incorporated into an RTA apparatus, which may be a lampannealing apparatus, while controlling the temperature to the roomtemperature and the atmosphere to the atmosphere of predominantly Ar,admixed with a small amount of O₂. Next, the flow rate of Ar is reducedrapidly and the temperature is raised also rapidly to about 600° C. Byholding the temperature at 600° C. for 90 seconds, the PLZT film 34undergoes a crystallization. In the foregoing RTA process, theconcentration of O₂ is changed variously as represented in TABLE III.

[0088] After the RTA process, the temperature is lowered and theconcentration of Ar in the atmosphere is increased. The substrate 31 isthen taken out from the RTA apparatus when the temperature is reachedbelow about 350° C. TABLE III RUN 1st RTA 2nd RTA orientation (%) No.600° C. 90s 725° C. 20s O(100) O(101) O(111) 1 O₂ 0.2% without 2.4 0.397.3 2 O₂ 1.0% without 1.3 0.1 98.6 3 O₂ 5.0% without 1.7 0.1 98.2 4 O₂0.2% O₂ 100% 2.2 0.3 97.5 5 O₂ 1.0% O₂ 100% 1.4 0.1 98.5 6 O₂ 5.0% O₂100% 2.4 0.1 97.5

[0089] As represented in TABLE III, some of the samples (No.4-No.6) arefurther subjected to an oxidizing process conducted at 725° C. for 20seconds with an RTA temperature profile set to 125° C./sec forcompensating for the oxygen defects formed in the PLZT film 34.

[0090]FIG. 4B shows the temperature profile of the second RTA processconducted in the oxidizing atmosphere.

[0091] Referring to FIG. 4B, the substrate 31 thus processed in thefirst RTA process is incorporated into an RTA apparatus, similar to theRTA apparatus used in the process of FIG. 4A while controlling thetemperature to the room temperature and flowing O₂ with a flow rate of20 SLM. Next, the flow rate Of O₂ is reduced rapidly and the temperatureis raised also rapidly to about 725° C. By holding the temperature at725° C. for 20 seconds, the oxygen defects in the crystallized PLZT film34 are effectively compensated for by oxygen.

[0092] After the RTA process, the temperature is lowered and theconcentration of O₂ in the atmosphere is increased. The substrate 31 isthen taken out from the RTA apparatus when the temperature is reachedbelow about 350° C.

[0093] It should be noted that the PLZT film 34 thus formed by asputtering process contains characteristically low concentration C(carbon) as compared with the PLZT film formed by a sol-gel process.

[0094] After the formation of the PLZT film 34, an upper electrode 35 ofPt is formed on the PLZT film 34 by a D.C. sputtering process conductedat the room temperature as represented in TABLE IV with a thickness ofabout 200 nm. As represented in TABLE IV, the formation of the upperelectrode 35 is achieved in an Ar plasma by setting the D.C. plasmapower to about 1.0 kW. In the example of TABLE IV, the Ar partialpressure is set to 0.7 Pa and the sputtering is continued for about 109seconds. TABLE IV Ar pressure RF power duration thickness (Pa) (kW)(second) (nm) Pt 0.7 1.0 109 200

[0095] Next, in the step of FIG. 3B, the upper electrode 35 and the PLZTfilm 34 are subjected to a plasma etching process and the desiredferroelectric capacitor 30 is obtained.

[0096]FIGS. 5A and 5B show the microstructure of the PLZT film 34corresponding to the Run No.4 before the upper electrode 35 is provided.As represented in TABLE III, the Run No.4 includes a crystallizationprocess of the PLZT film 34 conducted in an mixed atmosphere of Ar andO₂ in the first RTA process with the concentration of O₂ set to 0.2%,followed by the second RTA process of oxidizing annealing processconducted in the 100% O₂ atmosphere.

[0097] Referring to FIG. 5A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure with variouslychanging grain size, including large crystal grains having a graindiameter of as much as 200 nm. In the cross-sectional morphologyrepresented in FIG. 5B, it can be seen that the microstructure isgranular and the columnar microstructure is not recognized.

[0098]FIGS. 6A and 6B show the microstructure of the PLZT film 34corresponding to the Run No.5 before the upper electrode 35 is provided.As represented in TABLE III, the Run No.5 includes a crystallizationprocess of the PLZT film 34 conducted in an mixed atmosphere of Ar andO₂ in the first RTA process with the concentration of O₂ set to 1.0%,followed by the second RTA process of oxidizing annealing processconducted in the 100% O₂ atmosphere.

[0099] Referring to FIG. 6A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure similar to thatof FIG. 5A with variously changing grain size, including large crystalgrains having a grain diameter of as much as 200 nm. In thecross-sectional morphology represented in FIG. 6B, it can be seen thatthe microstructure has changed from granular to columnar.

[0100] Another interesting point to note in FIGS. 6A and 6B is thatlarge grains are generally granular and do not show the columnarmicrostructure, while small grains do show the columnar microstructure.Further, the large grains of FIGS. 6A and 6B, and also the grains ofFIGS. 5A and 5B, include little pinholes on the surface, while the smallgrains of FIGS. 6A and 6B do have some pinholes per each grain. As willbe explained later, these pinholes are believed to indicate the locationwhere the crystal is strained or deformed as a result of the existenceof the oxygen defect. In the specimen that have been subjected to thesecond RTA process as in the case of the Run No.4-6, the number of thepinholes is reduced as compared with the specimen of the Run No.1-3, aswill be explained below.

[0101]FIGS. 7A and 7B show the microstructure of the PLZT film 34corresponding to the Run No.6 before the upper electrode 35 is provided.As represented in TABLE III, the Run No.6 includes a crystallizationprocess of the PLZT film 34 conducted in an mixed atmosphere of Ar andO₂ in the first RTA process with the concentration of O₂ set to 5.0%,followed by the second RTA process of oxidizing annealing processconducted in the 100% O₂ atmosphere.

[0102] Referring to FIG. 7A showing the surface morphology, it can beseen that the PLZT film 34 has a uniform granular microstructurecharacterized by a generally uniform and small grain diameter of lessthan 200 nm. In the example of FIG. 7A, it appears that the PLZT crystalgrains have a grain diameter of about 100 nm in average. In thecross-sectional morphology represented in FIG. 7B, it can be seen thatthe PLZT film 34 has a clear columnar microstructure extendingperpendicularly to the principal surface of the underlying Pt electrode33. Because of the columnar growth of the individual PLZT crystalgrains, it can be seen that each crystal grain of FIG. 7A is separatedfrom neighboring crystal grains by a minute gap defining the grainboundary.

[0103] Thus, by comparing the morphology of FIGS. 5A, 6A and 7A, orFIGS. 5B, 6B and 7B, it can be seen that the grain diameter of the PLZTcrystals changes sharply with the oxygen concentration in the atmosphereused for the first RTA process. It should be noted that such a Ti-phaseis formed as a result of the diffusion of the Ti atoms from the Ti layer33A through the Pt lower electrode 33. Due to the fact that the Ti-phaseis oxidized already during the crystallization process of the PLZT film34, there occurs no further oxidation in the Ti-phase and the peeling ofthe PLZT film 34 is positively eliminated.

[0104]FIGS. 8A and 8B show the microstructure of the PLZT film 34corresponding to the Run No.1 before the upper electrode 35 is provided.As represented in TABLE III, the Run No.1 includes a crystallizationprocess of the PLZT film 34 conducted in an mixed atmosphere of Ar andO₂ in the first RTA process with the concentration of O₂ set to 0.2%,while there is no second RTA process conducted in the 100% O₂ atmospherefor compensating for the oxygen deficiency.

[0105] Referring to FIG. 8A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure, with themajority of the crystal grains having a size exceeding about 200 nm. Inthe cross-sectional morphology represented in FIG. 8B, it can be seenthat the microstructure is granular and the columnar microstructure isnot recognized.

[0106]FIGS. 8A and 8B further indicates that each of the PLZT crystalgrains has a somewhat clouded appearance, while it is believed that thisclouded appearance indicates the existence of crystal defects caused byoxygen deficiency.

[0107]FIGS. 9A and 9B show the microstructure of the PLZT film 34corresponding to the Run No.2 before the upper electrode 35 is provided.As represented in TABLE III, the Run No.2 includes a crystallizationprocess of the PLZT film 34 conducted in an mixed atmosphere of Ar andO₂ in the first RTA process with the concentration of O₂ set to 1.0%.Similarly to Run No.1 of FIGS. 8A and 8B, there is no second RTA processconducted in the 100% O₂ atmosphere for compensating for the oxygendeficiency.

[0108] Referring to FIG. 9A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure, with themajority of the crystal grains having a grain diameter of about 200 nm.In the cross-sectional morphology represented in FIG. 9B, it can be seenthat there appears a columnar microstructure, contrary to themicrostructure of FIG. 8B.

[0109]FIGS. 9A and 9B further indicates that each of the PLZT crystalgrains has a somewhat clouded appearance similarly to the microstructureof FIGS. 8A and 8B, wherein this clouded appearance of the crystalgrains is believed to indicate the existence of crystal defects causedby oxygen deficiency.

[0110] Further, FIGS. 10A and 10B show the microstructure of the PLZTfilm 34 corresponding to the Run No.3 before the upper electrode 35 isprovided. As represented in TABLE III, the Run No.3 includes acrystallization process of the PLZT film 34 conducted in an mixedatmosphere of Ar and O₂ in the first RTA process with the concentrationof O₂ set to 5.0%. Similarly to Run No.1 of FIGS. 8A and 8B, there is nosecond RTA process conducted in the 100% O₂ atmosphere for compensatingfor the oxygen deficiency.

[0111] Referring to FIG. 10A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure, with themajority of the crystal grains having a grain diameter of less than 200nm. In the average, it appears that the PLZT crystal grains have anaverage diameter of about 150 nm. In the cross-sectional morphologyrepresented in FIG. 10B, it can be seen that there appears a distinctcolumnar microstructure, similar to that of FIG. 7B.

[0112]FIGS. 10A and 10B further indicates that each of the PLZT crystalgrains has a somewhat clouded appearance similarly to the microstructureof FIGS. 8A and 8B or FIGS. 9A and 9B, wherein this clouded appearanceof the crystal grains is believed to indicate the existence of crystaldefects caused by oxygen deficiency.

[0113] Further, FIGS. 11A and 11B show the microstructure of the PLZTfilm 34 before the upper electrode 35 is provided, wherein FIGS. 11A and11B show the crystallization process of the PLZT film 34 conducted in anAr atmosphere in the first RTA, followed by the second RTA processconducted in the 100% O₂ atmosphere at 725° C. for compensating for theoxygen deficiency.

[0114] Referring to FIG. 11A showing the surface morphology, it can beseen that the PLZT film 34 has a granular microstructure, with agenerally uniform crystal grain diameter of about 200 nm. In thecross-sectional morphology represented in FIG. 11B, on the other hand,it can be seen that there is no columnar microstructure in the PLZT film34.

[0115] As a result of the second RTA process for compensating O₂, theclouded appearance of the crystal grains is disappeared, and instead,there appear a pinhole structure in the surface of the PLZT crystalgrains.

[0116] Further, FIG. 12 shows the surface morphology of the PLZT film 34in the case in which the first RTA step is conducted in a pure Aratmosphere. No second RTA process is applied.

[0117] Referring to FIG. 12, it can be seen that the crystal grains havean average diameter of about 200 nm or more, contrary to the case ofconducting the first RTA process in the oxygen-containing atmosphere. Inview of the absence of the second RTA process, the microstructure ofFIG. 12 still contains a large amount of oxygen defects, while theexistence of the oxygen defects is represented as a result of theclouded or stained view of the crystal grains.

[0118]FIG. 13 shows the switching electric charges Q_(sw) of theferroelectric capacitor 30 of FIG. 3B for various oxygen concentrationsused in the first RTA process. In FIG. 13 it should be noted that allthe experimental data are for the specimen subjected to the first andsecond RTA processes as represented in FIGS. 4A and 4B.

[0119] Referring to FIG. 13, it can be seen that a value of Q_(sw)exceeding 25 μC/cm² is achieved up to the concentration level of O₂ ofabout 50% in volume. When the O₂ concentration level exceeds 50%, on theother hand, the value of the switching electric charges drops sharply.

[0120]FIG. 14 shows the 90%-saturation voltage V_(90%) of theferroelectric capacitor 30, wherein the 90%-saturation voltagerepresents the voltage applied across the upper and lower electrodes 35and 33 so as to cause a 90% saturation in the polarization of theferroelectric capacitor insulation film 34. See FIG. 2. In FIG. 14, too,all the experimental data are for the specimen subjected to the firstand second RTA processes as represented in FIGS. 4A and 4B.

[0121] Referring to FIG. 14, it can be seen that a low voltage of almost3 V is realized for the 90%-saturation voltage, as long as the O₂concentration level in the atmosphere of the first RTA process does notexceed 50% in volume. On the other hand, when a pure O₂ atmosphere isused in the first RTA process, the 90%-saturation voltage increasessharply and reaches about 4 V or more.

[0122]FIG. 15 shows the volume fraction of the <111>-oriented crystalgrains in the PLZT film 34, as a function of the O₂ concentration levelin the first RTA process. Similarly as before, all the data of FIG. 15are for the specimen subjected to the first RTA process and the secondRTA process as represented in FIGS. 4A and 4B.

[0123] Referring to FIG. 15, it can be seen that the volume fraction ofthe <111>-oriented crystal grains decreases gradually with increasing O₂concentration level in the atmosphere used in the first RTA process,until the O₂ concentration level reaches about 50% in volume. When theO₂ concentration level exceeds the foregoing level of 50%, on the otherhand, the proportion of the <111>-oriented crystal grains decreasessharply.

[0124] Further, FIG. 16 shows the volume fraction of the <100>-orientedcrystal grains in the PLZT film 34, as a function of the O₂concentration level in the first RTA process. Similarly as before, allthe data of FIG. 16 are for the specimen subjected to the first RTAprocess and the second RTA process as represented in FIGS. 4A and 4B.

[0125] Referring to FIG. 16, it can be seen that the volume fraction ofthe <100>-oriented crystal grains increases gradually with increasing O₂concentration level in the atmosphere used in the first RTA process,until the O₂ concentration level reaches about 50% in volume. When theO₂ concentration level exceeds the foregoing level of 50%, on the otherhand, the proportion of the <100>-oriented crystal grains increasessharply.

[0126] Summarizing above, it is desirable, in view of eliminating thepeeling of the ferroelectric film 34 of the ferroelectric capacitor 30to conduct the first RTA process in the atmosphere containing a smallamount of oxidizing gas in addition to an inert gas, wherein theconcentration of the oxidizing gas is preferably larger than about 1%but not exceeding about 50%, in view of the electric property of theobtained ferroelectric film and hence the performance of theferroelectric capacitor. The ferroelectric film thus processed with sucha partially oxidizing atmosphere in the first RTA process ischaracterized by the columnar microstructure of the crystal grainshaving the <111>-orientation and a grain size of about 200 nm or less,in average about 150 nm.

[0127] As the atmosphere during the crystallization is stillpredominantly inert in the present invention, in spite of the fact thatthe oxidizing gas is admixed to the non-oxidizing gas, there occurs adensification in the lower electrode during the crystallization processof the ferroelectric film, and the problem of mutual diffusion of Pt andO at the interface between the ferroelectric film and underlying lowerelectrode is also suppressed.

[0128] [SECOND EMBODIMENT]

[0129] Next, a second embodiment of the present invention will bedescribed with reference to FIGS. 3A and 3B used for explaining thefirst embodiment.

[0130] Referring to FIG. 3A, the present embodiment forms the PLZT film34 on the lower electrode 33 of Pt by a sputtering process with athickness of about 200 nm similarly as in the case of the firstembodiment, except that the present embodiment carries out acrystallizing annealing process of the PLZT film 24 under a reduced O₂pressure environment. In a typical example, the total pressure of the O₂atmosphere is set to about 1 Torr and the crystallization of the PLZTfilm 34 is conducted in the O₂ atmosphere at a temperature of 650° C.for 2 minutes.

[0131] After the crystallization process, the PLZT film 34 is subjectedto a thermal annealing process conducted in an O₂ atmosphere of theordinary pressure (760 Torr) at the temperature of 750° C. for 1 minute.

[0132] After the formation and processing of the PLZT film 34 as notedabove, a film of IrO₂ is deposited on the PLZT film 34 to form the upperelectrode layer 35 as represented in FIG. 3A, followed by a patterningprocess conducted in the step of FIG. 3B to form the upper electrodepattern designated also by the numeral 35. The upper electrode layer 35of IrO₂ is subjected to a recovery annealing process conducted in an O₂atmosphere at 650° C. for about 60 minutes, and the PLZT film 34 isfurther subjected to a patterning process to form the ferroelectriccapacitor insulation film also designated by the reference numeral 34 inFIG. 3B.

[0133] According to the crystallization process conducted in such areduced pressure environment of O₂, the oxidation of the lower electrode33 of Pt is avoided and there occurs a densification in the electrode 33similarly to the case of the first embodiment. Thereby, the migration ofTi from the underlying adhesion layer 33A to the surface of the lowerelectrode 33 is suppressed and the growth of the PLZT film 34 in the<111>-direction is facilitated.

[0134] By using a small amount of O₂ in the crystallizing process, theTi atoms that have reached the surface of the lower electrode 33 areoxidized to form a chemically stable compound. Thereby, the problem ofcracking at the interface between the lower electrode 33 and the PLZTfilm 34 due to the volume increase associated with the oxidation of Tiis effectively avoided.

[0135]FIG. 17 shows the volume fraction of the <111>-oriented crystalgrains in the PLZT film 34 of the ferroelectric capacitor of FIG. 3Bwith respect to the <101>- or <100>-oriented crystal grains according toa second embodiment of the present invention wherein the presentembodiment carries out the crystallization process before the upperelectrode layer 35 is formed.

[0136] As represented in FIG. 17, a volume fraction of almost 100% isconducted at the temperature of 600° C. or higher, indicating that thereoccurs an effective densification in the lower electrode 33 of Pt as aresult of the crystallization process of the PLZT film 34 thus conductedin a reduced total pressure environment of O₂ atmosphere. Further, theuse of the O₂ atmosphere effectively eliminates the cracking of the PLZTfilm 34 at the interface to the lower electrode 33. In the experiment ofFIG. 17, it should be noted that the PLZT film 34 showed nocrystallization when the temperature is set to 500° C. or less. When thetemperature is set to 550° C., a proportion of 77.7% is obtained for the<111>-oriented crystal grains.

[0137]FIG. 18 shows the volume fraction of the <111>-oriented PLZTcrystal grains in the PLZT film 34 for various total pressures of the O₂atmosphere used in the crystallization process of the PLZT film 34.

[0138] Referring to FIG. 18, it can be seen that a proportion of almost100% is obtained for the <111>-oriented crystal grains in the PLZT film34 when the total pressure of the O₂ atmosphere used for crystallizingthe PLZT film 34 is set to be about 40 Torr or less. On the other hand,the use of excessively low O₂ pressure less than 0.5 Torr in thecrystallization process may cause the problem of cracking of the PLZTfilm 34 as explained previously. Thus, it is thought preferable to setthe total pressure of the O₂ atmosphere to be about 1 Torr or higher.

[0139]FIG. 19 shows the switching electric charge Q_(sw) for theferroelectric capacitor thus obtained, wherein the vertical axisrepresents the switchinelectric charge Q_(sw) while the horizontal axisrepresents the temperature used for crystallizing the PLZT film 34. Theresult of FIG. 19 is for the case in which the crystallization processis conducted under a reduced pressure environment in which the totalpressure is set to 1 Torr. FIG. 19 shows the minimum Q_(sw) valueobserved-by open diamonds and the maximum Q_(sw) value by soliddiamonds.

[0140] As can be seen from FIG. 19, a value of between about 25 μC/cm²and about 30 μC/cm² is obtained for the switching electric charge Q_(sw)when the crystallization process is conducted at 650° C., wherein thisvalue of Q_(sw) is substantially improved as compared with the case inwhich the PLZT film 34 is annealed in an O₂ atmosphere of ordinarypressure. See FIG. 13.

[0141]FIG. 20 shows the 90%-saturation voltage of the ferroelectriccapacitor thus formed for various temperatures used for crystallizingthe PLZT film 34. Similarly to the case of FIG. 19, the crystallizationof the PLZT film 34 was conducted in the reduced pressure environment ofO₂ in which the total pressure is set to 1 Torr. In FIG. 20, the opendiamonds represent the minimum observed value of the 90%-saturationvoltage, while the solid diamonds represent the maximum observed value.

[0142] As can be seen clearly from FIG. 20, it is possible to reduce the90%-saturation voltage to be smaller than 5V, by conducting thecrystallization process at 650° C.

[0143] In the present embodiment, the inventor of the present inventionhas made an interesting discovery in that appearance of a columnarcrystal of PLZT having a vertically split structure as representedschematically in FIG. 21A, of which occurrence is observed occasionallywhen the crystallizing process is conducted in the mixed atmosphere ofAr and O₂ of ordinary total pressure, is eliminated substantiallycompletely when the crystallization process is conducted in a reducedpressure environment as taught in the present embodiment.

[0144] In the split columnar crystal of FIG. 21A, it should be notedthat the upper part of the crystal grain designated in FIG. 21A by anumeral 34 a has an orientation generally different from the desired<111>-orientation for the lower part designated by a reference numeral34 b, and the existence of such a split crystal grain 34 a has causedthe effect of reducing the total value of the switching electric chargeof the ferroelectric capacitor. It is believed that such a split crystalgrain 34 a is formed due to the crystal growth occurring from thesurface of the columnar crystal where Pb in the PLZT crystal grain tendsto form a hydroxide or similar compound that act as the nuclei ofcrystal growth as represented in FIG. 21A by a reference numeral 34 x.

[0145] By implementing the crystallization process of the PLZT film 34in the reduced pressure environment, Pb tends to escape from the part ofthe PLZT layer 34 by evaporation as represented schematically in FIG.21B, and the formation of Pb compound 34 x, and hence the growth of thesplit crystal grain 34 a using such a Pb compound 34 x as the nuclei, iseffectively eliminated.

[0146] Further, the use of the reduced pressure environment as taught inthe present embodiment is advantageous in view point of improving thereproducibility of the crystallization process, as the supply of a freshO₂ atmosphere into a vacuum or reduced pressure environment can becarried out much more stably as compared with the case the freshlysupplied O₂ atmosphere has to replace or purge the existing atmosphereas in the case of conducting the crystallization process under anordinary pressure environment.

[0147] In the present embodiment, it should be noted that the supply ofO₂ in the crystallization process can be made also in the form of amixed gas of O₂ and an inert gas such as Ar. It seems that it isimportant, in any of the present embodiment as well as in the previousembodiment, to supply a limited amount or moles of O₂ just enough fordeactivating the Ti atoms migrated to the surface of the lower electrode33. From this view point, the total pressure of the O₂ atmosphere usedfor crystallizing the PLZT film 34, or the partial pressure of the O2 inthe Ar—O₂ atmosphere in the case of the previous embodiment, should becontrolled depending on the Ti atoms on the surface of the lowerelectrode 33.

[0148] Further, in the present embodiment, in which the crystallizationprocess is conducted in a reduced pressure environment, the supply of O₂to the ferroelectric film is achieved more efficiently than in the caseof conducting the crystallization under an atmospheric pressure, and itis possible to conduct the crystallizing step and the oxidizing stepsimultaneously by raising the temperature to 650° C. or more rapidly orstepwise. Further, it is possible to conduct the oxidizing step under areduced atmosphere of oxygen.

[0149] [THIRD EMBODIMENT]

[0150] FIGS. 22A-22R show the fabrication process of a semiconductordevice according to a third embodiment of the present invention.

[0151] Referring to FIG. 22A, a p-type well 41A and an n-type well 41Bare formed on a Si substrate 41, which may be any of the p-type orn-type, wherein the Si substrate 41 is covered by a field oxide film 42defining an active region in each of the p-type well 41A and the n-typewell 41B.

[0152] Next, a gate oxide film 43 is formed on the active region of thep-type well 41A and also on the active region of the n-type well 41B,and a p-type polysilicon gate electrode 44A is formed on the gate oxidefilm 43 in the p-type well 41A. Similarly, an n-type polysilicon gateelectrode 44B is formed on the gate oxide film 43 in correspondence tothe n-type well 41B. In the illustrated example, polysiliconinterconnection patterns 44C and 44D are formed further on the fieldoxide film 42 similarly to the polysilicon gate electrodes 44A and 44B.

[0153] In the structure of FIG. 22A, there are formed n-type diffusionregions 41 a and 41 b in the active region of the p-type well 41A byconducting an n-type impurity element by an ion implantation process,while using the gate electrode 44A and the side wall insulation filmsthereon as a self-alignment mask. Similarly, p-type diffusion regions 41c and 41 d are formed in the active region of the n-type well 41B by anion implantation process of a p-type impurity element, while using thegate electrode 44B and the side wall insulation films thereon as aself-alignment mask.

[0154] The process so far is nothing but an ordinary CMOS process.

[0155] Next, in the step of FIG. 22B, an SiON film 45 is deposited onthe structure of FIG. 22A by a CVD process with a thickness of about 200nm, and an SiO₂ film 46 is further deposited on the SiON film 45 by aCVD process with a thickness of about 1000 nm.

[0156] Further, in the step of FIG. 22C, the SiO₂ film 46 is subjectedto a CMP process while using the SiON film 45 as a polishing stopper,and contact holes 46A-46D are formed in the step of FIG. 22D in the SiO₂film 46 thus planarized such that the diffusion regions 41 a, 41 b, 41 cand 41 d are exposed by the contact holes 46A, 46B, 46C and 46D. In theillustrated example, the SiO₂ film 46 is further formed with a contacthole 46E so as to expose the interconnection pattern 44C.

[0157] Next, in the step of FIG. 22E, a W layer 47 is deposited on thestructure of FIG. 22D so as to fill the contact holes 46A-46E, whereinthe W layer 47 thus deposited is subjected to a CMP process while usingthe SiO₂ film 46 as a stopper. As a result of the polishing process,there are formed W plugs 47A-47E respectively in correspondence to thecontact holes 46A-46E.

[0158] Next, in the step of FIG. 22G, an oxidization stopper film 48 ofSiN and an SiO₂ film 49 are deposited consecutively on the structure ofFIG. 22F respectively with the thicknesses of 100 nm and 130 nm,followed by a thermal annealing process conducted in an N₂ atmosphere at650° C. for about 30 minutes. The thermal annealing process is conductedso as to thoroughly remove gases from the structure thus formed.

[0159] Next, in the step of FIG. 22H, a Ti film 50 and a Pt film 51 aredeposited consecutively on the SiO₂ film 49 with respective thicknessesof 20 nm and 175 nm by a sputtering process, which may be conductedaccording to the condition represented in TABLE I. The Ti film 50 andthe Pt film 51 thereon constitute a lower electrode layer of theferroelectric capacitor to be formed.

[0160] After the deposition of the Ti film 50 and the Pt film 51, aferroelectric film 52 of PZT or PLZT is sputter-deposited in the step ofFIG. 22H under the condition of TABLE II, wherein the ferroelectric film52 may contain Ca or Sr.

[0161] Further, in the step of FIG. 22H, the ferroelectric film 52 issubjected to a crystallization process first by an RTA process conductedin an mixed atmosphere containing 1-50% of oxidizing gas, followed by anoxidizing process by an RTA process conducted in an oxidizingatmosphere, as represented in the Run No.5 or 6 of TABLE III.Alternatively, the crystallization process of the ferroelectric film 52may be conducted in a reduced pressure environment containing O₂ asdescribed already.

[0162] Further, in the step of FIG. 22H, a Pt film 53 is deposited onthe ferroelectric film 52 thus processed as an upper electrode layer bya sputtering process conducted according to the condition of TABLE IV.

[0163] Next, in the step of FIG. 22I, a resist pattern is formed on theupper electrode layer 53, followed by the patterning of the upperelectrode layer 53 by a dry etching process to form an upper electrodepattern 53A on the ferroelectric film 52. In the step of FIG. 22I, itshould further be noted that the ferroelectric film 52 is subjected,after the foregoing sputtering and patterning of the upper electrodepattern 53A, to a recovery annealing process conducted in an O₂atmosphere at 650° C. for 60 minutes so as to recover any damages causedin the ferroelectric film 52 as a result of the foregoing sputtering andpatterning processes.

[0164] Next, in the step of FIG. 22J, a resist pattern having a shapecorresponding to the shape of the capacitor insulation film to beformed, is formed on the ferroelectric insulation film 52, and theferroelectric insulation film 52 is subjected to a dry etching processwhile using the foregoing resist pattern as a mask. As a result, adesired capacitor insulation film pattern 52A is formed on theunderlying lower electrode layer 51. Further, an encapsulating layer 52Bis formed on the lower electrode layer 51 by a ferroelectric materialhaving a composition substantially identical with that of the materialconstituting the ferroelectric film 52, by conducting a sputteringprocess with a thickness of about 20 nm. The encapsulating layer 52Bthus deposited is then annealed by an RTA process in the O₂ atmosphereat 700° C. for 60 seconds with a temperature profile of about 125°C./min. The encapsulating layer 52B thereby protects the ferroelectriccapacitor insulation film pattern 52A from reduction.

[0165] Next, in the step of FIG. 22K, a resist pattern is formed on thelower electrode layer 51 so as to cover the encapsulating layer 52B witha pattern corresponding to the lower electrode pattern to be formed.Further, by conducting a dry etching process on the foregoingencapsulating layer 52B and the underlying Pt and Ti films 50 and 51underneath the encapsulating layer 52B by a dry etching process, a lowerelectrode pattern 51A is formed.

[0166] After the formation of the lower electrode pattern 51A, theresist pattern is removed in the step of FIG. 22K, and the damages thatare introduced into the ferroelectric capacitor insulation film 52Aduring the dry etching process of the lower electrode pattern 51A arerecovered by conducting a recovery annealing process in an O₂ atmosphereat 650° C. for 60 minutes.

[0167] Next, in the step of FIG. 22L, an SiO₂ film 54 is deposited onthe structure of FIG. 22K by a CVD process, typically with a thicknessof about 200 nm, followed by a formation of an SOG film 55 thereon,wherein the SOG film 55 smoothes any sharp steps formed on theunderlying SiO₂ film 54. The SiO₂ film 54 and the SOG film 55 formtogether an interlayer insulation film 56.

[0168] Next, in the step of FIG. 22M, contact holes 56A and 56B areformed in the interlayer insulation film 56 so as to expose the upperelectrode pattern 53A and the lower electrode pattern 51A respectively,and contact holes 56C and 56D are formed further in the step of FIG. 22Nin the interlayer insulation film 56 so as to expose the W plugs 47B and47D respectively through the underlying SiO₂ film 49 and the SiN film48. Further, in the step of FIG. 22M, a recovery annealing process isconducted, after the dry etching process for forming the contact holes56A and 56B,in an O₂ atmosphere at 550° C. for 60 minutes. As a resultof the recovery annealing process, any damages introduced into theferroelectric film patterns 52A and 52B during the dry etching processare eliminated.

[0169] Next, in the step of FIG. 22O, a local interconnection pattern57A is formed by a TiN film such that the local interconnection pattern57A connects the contact hole 56A and the contact hole 56C electrically.Further, a similar local interconnection pattern 57B and 57C are formedon the contact holes 56B and 56C.

[0170] Next, in the step of FIG. 22P, an SiO₂ film 58 is formed on thestructure of FIG. 22O, and contact holes 58A, 58B and 58C are formed inthe SiO₂ film in the step of FIG. 17Q so as to expose the W plug 47A,the local interconnection pattern 57B and the W plug 47C, respectively.

[0171] Further, in the step of FIG. 22R, electrodes 59A, 59B and 59C areformed respectively in correspondence to the contact holes 58A, 58B and58C.

[0172] Further, the process of forming the interlayer insulation filmand the interconnection patterns may be repeated as desired, to form amultilayer interconnection structure.

[0173] According to the present embodiment, the peeling of theferroelectric capacitor insulation film pattern 52A is eliminated byconducting the crystallization process in an atmosphere containing aninert gas and an oxidizing gas. By using a limited amount of O₂ in thecrystallizing process, the microstructure of the ferroelectric capacitorinsulation film pattern 52A is controlled to have a columnar structure,with small crystal grains, typically having a generally uniform graindiameter of less than about 200 nm, or about 150 nm in average. Theferroelectric capacitor insulation film pattern 52A having such acolumnar microstructure has the desired <111> orientation and ischaracterized by a large switching electrical charges Q_(sw) and smallsaturation voltage.

[0174] In the crystallization process conducted in the partiallyoxidizing atmosphere, it should be noted that the oxidizing gas is notlimited to O₂ but other gas containing oxygen such as N₂O, NO, NO₂, andthe like may be used as well. Further, the inert gas used in thepartially oxidizing atmosphere is not limited to Ar but N₂, He, Ne, Xe,and the like may also be used.

[0175] Further, it should be noted that the foregoing first and secondRTA steps may be conducted continuously in a single step, byinterrupting the supply of the inert gas and by increasing the oxygenconcentration in correspondence to the second RTA process.

[0176] Further, the ferroelectric film of the present invention is notlimited to the PZT or PLZT film described heretofore, but otherferroelectric material having the perovskite structure or a layered Bicompound may also be used.

[0177] Further, the present invention is not limited to the embodimentsdescribed heretofore, but various variations and modifications may bemade without departing from the scope of the present invention.

What is claimed is:
 1. A method of fabricating a semiconductor devicehaving a ferroelectric capacitor, comprising the steps of: forming anactive device element on a substrate; forming an insulation film oversaid substrate to cover said active device element; forming a lowerelectrode layer of said ferroelectric capacitor over said insulationfilm; forming a ferroelectric film on said lower electrode layer as acapacitor insulation film of said ferroelectric capacitor; crystallizingsaid ferroelectric film by applying a thermal annealing process in anatmosphere containing a non-oxidizing gas and an oxidizing gas; andforming an upper electrode layer on said ferroelectric film.
 2. A methodas claimed in claim 1, wherein said step of forming said lower electrodelayer includes a step of depositing a Ti layer and a Pt layerconsecutively.
 3. A method as claimed in claim 1, wherein said step ofcrystallizing said ferroelectric film is conducted by setting thecomposition of said atmosphere such that said atmosphere contains saidoxidizing gas with a fraction of 1-50% in volume.
 4. A method as claimedin claim 1, wherein said non-oxidizing gas is selected from a groupconsisting of Ar, He, Ne, Xe and N₂.
 5. A method as claimed in claim 1,wherein said oxidizing gas is selected from a group consisting of O₂,N₂O, NO and NO₂.
 6. A method as claimed in claim 1, wherein said step ofcrystallizing said ferroelectric film is conducted by a rapid thermalannealing process.
 7. A method as claimed in claim 1, wherein said stepof forming said step of forming said ferroelectric film comprises thestep of forming said ferroelectric film by a sputtering process.
 8. Amethod as claimed in claim 7, wherein said ferroelectric film has aperovskite structure.
 9. A method as claimed in claim 8, wherein saidferroelectric film is a film of zirconate titanate of Pb.
 10. A methodas claimed in claim 1, further comprising the step, after said step ofcrystallizing said ferroelectric film, of oxidizing said ferroelectricfilm in an oxidizing atmosphere.
 11. A method as claimed in claim 1,wherein said step of crystallizing said ferroelectric film is conductedunder a reduced total pressure.
 12. A method of fabricating asemiconductor device having a ferroelectric capacitor, comprising thesteps of: forming an active device element on a substrate; forming aninsulation film over said substrate to cover said active device element;forming a lower electrode layer of said ferroelectric capacitor oversaid insulation film; forming a ferroelectric film on said lowerelectrode layer as a capacitor insulation film of said ferroelectriccapacitor; crystallizing said ferroelectric film by applying a thermalannealing process in an atmosphere of an oxidizing gas under a reducedtotal pressure smaller than an atmospheric pressure; and forming anupper electrode layer on said ferroelectric film.
 13. A method asclaimed in claim 1 wherein said oxidizing gas is O₂ and wherein saidtotal pressure is set in the range between 1 Torr and 40 Torr.
 14. Amethod of fabricating a semiconductor device having a ferroelectriccapacitor, comprising the steps of: forming an active device element ona substrate; forming an insulation film over said substrate to coversaid active device element; forming a lower electrode layer of saidferroelectric capacitor over said insulation film, said lower electrodelayer including a layer part containing Ti atoms; forming aferroelectric film on said lower electrode layer as a capacitorinsulation film of said ferroelectric capacitor; crystallizing saidferroelectric film by applying a thermal annealing process in anatmosphere of an oxidizing gas; and forming an upper electrode layer onsaid ferroelectric film, wherein said step of crystallizing saidferroelectric film is conducted by supplying O₂ controlled to cause anoxidation in said Ti atoms reached a surface of said lower electrodefrom said layer part containing Ti atoms.
 15. A semiconductor device,comprising: a substrate; an active device element formed on saidsubstrate; an insulation film provided over said substrate to cover saidactive device element; a lower electrode provided over said insulationfilm; a ferroelectric film provided on said lower electrode, saidferroelectric film having a columnar microstructure extending from aninterface between said lower electrode and said ferroelectric film in adirection substantially perpendicular to a principal surface of saidlower electrode, said ferroelectric film essentially consisting ofcrystal grains having a generally uniform grain diameter of less thanabout 200 nm; and an upper electrode provided on said ferroelectricfilm.
 16. A semiconductor device as claimed in claim 15, wherein saidcrystal grains constituting said ferroelectric film have an averagediameter of about 150 nm.
 17. A semiconductor device as claimed in claim15, wherein said lower electrode comprises a Ti layer and a conductorlayer provided further on said Ti layer.
 18. A semiconductor device asclaimed in claim 17, wherein said conductor layer is formed of Pt.
 19. Asemiconductor device as claimed in claim 17, wherein said ferroelectricfilm has a perovskite structure.
 20. A semiconductor device as claimedin claim 19, wherein said ferroelectric film comprises a zirconatetitanate of Pb.